Cordic based parallel/pipelined architecture for the Hough transform

نویسندگان

  • Javier D. Bruguera
  • Nicolás Guil Mata
  • Tomás Lang
  • Julio Villalba
  • Emilio L. Zapata
چکیده

We present the design of parallel architectures for the computation of the Hough transform based on application-specific CORDIC processors. The design of the circular CORDIC in rotation mode is simplified by the a priori knowledge of the angles participating in the transform and a high throughput is obtained through a pipelined design combined with the use of redundant arithmetic (carry save adders in this paper). Saving area is essential to the design of a pipelined CORDIC and can be achieved through the reduction in the number of microrotations and/or the size of the coefficient ROM. To reduce the number of microrotations we incorporate radix 4, when it is possible, or mixed radix (radix 2 and radix 4) in the design of the processor, achieving a reduction by half and 25% microrotations, respectively, with respect to a totally radix 2 implementation. Furthermore, if we allocate two circular CORDIC rotators into one processors then the size of the shared coefficient ROM is only 50% of the ROM of a design based on two separated rotators. Finally, we have also incorporated additional microrotations in order to reduce the scale factor to one. The result is a pipelined architecture which can be easily integrated in VLSI technology due to its regularity and modularity.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Design and Implementation of Digital Demodulator for Frequency Modulated CW Radar (RESEARCH NOTE)

Radar Signal Processing has been an interesting area of research for realization of programmable digital signal processor using VLSI design techniques. Digital Signal Processing (DSP) algorithms have been an integral design methodology for implementation of high speed application specific real-time systems especially for high resolution radar. CORDIC algorithm, in recent times, is turned out to...

متن کامل

A Complete Pipelined Parallel CORDIC Architecture for Motion Estimation

We propose a novel fully-pipelined parallel CORDIC architecture (CORDIC-DXT-ME) employing the DCT PseudoPhase Techniques for Motion Estimation. Its low computational complexity, O(N2) as compared with O ( N " ) of BKlI ME; makes it fascinating in real time applications. In addition, the DCT-based nature enables us to replace all multipliers by CORDICs with simple shift-and-add operations and t ...

متن کامل

A VLSI array architecture for Hough transform

In this article, an asynchronous array architecture for straight line Hough Transform (HT) is proposed using a scaling free modified CORDIC (CoOrdinate Rotation Digital Computer) unit as a basic Processing Element (PE). It exhibits four-fold angle parallelism by dividing the Hough space into four subspaces to reduce the computation burden to 25% of the conventional requirements. A distributed a...

متن کامل

A Complete Pipelined Parallel CORDIC Architecture For Motion Estimation - Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

In this paper, a novel fully pipelined parallel CORDIC architecture is proposed for motion estimation. Unlike other block matching structures, it estimates motion in the discrete cosine transform (DCT) transform domain instead of the spatial domain. As a result, it achieves high system throughput and low hardware complexity as compared to the conventional motion estimation design in MPEG standa...

متن کامل

A High-Throughput and Memory-Efficiency 2-D DCT Architecture Based on CORDIC Rotation

2-D Discrete Cosine Transform (DCT) applies on image data compression and saves more memories. In this paper, we use fast DCT algorithm, and propose a parallel-pipelined architecture to implement a 8 8× DCT/IDCT processor. This architecture involves two 8-point DCT processors, dual-bank of SRAM (128 words) and the coefficient ROM, three multiplexers, timing controller and 7-bit counter. The ker...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:
  • VLSI Signal Processing

دوره 12  شماره 

صفحات  -

تاریخ انتشار 1996